Facing the problems used to be existed in the parallel processing technology, previous invention (China patent pending number 00119472.0) had found the match of numbers of N+1 flows and N+1 sequences, and stated the matching of flow numbers and sequence numbers as necessary conditions of utility. Meanwhile, as for the goal of utility, previous invention of sequence net computers created the sequence net computer structure of N+1 programs. Sequence net computers support sequence net of N+1 programs without parameter constraints and the first step of utility was realized.
The utility of sequence net computers is further developed in this invention. This invention further converts the encapsulation capability of parallel programs of sequence net to sub-sequence net modules (hereinafter as Sub SN) which are featured with call capability and automatic return. Besides, multiple sequence net combination can be established with Sub SN call structure, so that the adaptability of sequence net computer structure and application models are further developed.
In FIG. 1, this invention set up the device structure of call sub-routines of single machine. In FIG. 2, sequence net structure of previous technology is shown and Sub SN is established. FIG. 3 and the figured followed are used to describe the structure of call Sub SN.
FIG. 1A is the sub-routine call in single machine. “Call” and “return” are two computer instructions, are elements of embedded structure of processing programs. In FIG. 1A, the call instruction 100 of program 101 can realize the call of a sub-routine 102. Call instruction 100 is embedded in original program 101, and contains entry port address parameters of sub-routine 102. After instruction 100 executed, the program is entering sub-routine 102. After the return instruction of sub-routine 102 was executed, the program is returned to original program 101 and the operation goes on.
Call instruction can be resolved into two parameters, call position and call parameter. Call position denotes the position in original program and is kept an ordered relation with other instructions in original program, irrelevant to sub-routine. Call parameter denotes the entry port address of sub-routine and is irrelevant to the structure of original program. Sub-routine module contains three parameters, i.e., entry port address, program body, and return instruction. Among which, the combination of “program body” and “return instruction” forms sub-routine. Hence, the process of “call instruction+program body+return instruction” is called “call sub-routine”. The hardware supporting call sub-routine is named call sub-routine device.
The actual construction of call sub-routine device is that the operations from single machine programs to call instructions and the operations of producing call position and call parameters. The operation on position is to transfer the contents of instruction counter to stack area. The operation of call parameters is to send parameters to instruction counter. Then the next instruction will take the parameter as address and to execute. When the sub-routine concluded, a return instruction was executed and the data in the stack are sent to instruction counter so that the next instruction will take it as address and execute. This process is corresponding to the return of original program and the execution continues. Obviously in the structure of single machine CPU, the construction of call sub-routine devices is diversified and some of them are shared by other instructions. In this invention, they are combined together and a unique featured sub-routine device is defined.
External features of call sub-routine are call position and sub-routine modules. The call instruction and called program (i.e. entry port address of call parameter and sub-routine) are connected as internal connection.
From the view point of original program, a call instruction can activate sub-routine device, call instruction provide the device with two parameters, position and parameters. In accordance with the position, call structure sub-routine device is to protect program address and to assign sub-routine entry port on the basis of call parameters. After sub-routine executed return instruction, call sub-routine processing program returns to its previous position.
The call program and return instruction of call sub-routine device use appropriate software and instruction hardware structure commonly used in single machine. Hence, the parts specific to call sub-routine device are the hardware structures including those used in call instruction, parameter transferring, and sub-routine initiation phase.
The informational relations between call sub-routine parts are “call position” of call instruction used to initiate sub-routine devices, “call parameters” used to transfer information inside call sub-routine devices and indicate the connection with sub-routine modules, and “sub-routine” including return instruction for returning back to original program. “Call position—call parameter—sub-routine” is the procedures of signal processing inside sub-routine devices.
FIG. 1B and FIG. 1C showed the relations between call position, call parameter, and sub-routine. From the standpoint of information, FIG. 1A showed the embedded relations between single machine call sub-routine devices. FIG. 1B showed that in the same call position of 108, different sub-routines can be called in different conditions of call parameter. FIG. 1C showed that in different call positions of 108, same sub-routine can be called in same condition of call parameter.
FIG. 1D is the schematic diagram of call sub-routine structure based on the description of call information. In single machine environment, call position, call parameter, and sub-routine module can form the structural characteristics, as shown in FIG. 1D. Among which, 108 is call position, 102 is sub-routine module, and 104 is a virtual bus structure. The function of virtual bus 104 is to transfer call parameter and realize the connection of position and sub-routine.
Call position is embedded in program 105. FIG. 1D indicated clearly the structural hierarchical relation between the set of call position 108 and the set of sub-routine 102. Of course, this hierarchical relation is just the relation in program structure and is serial in nature by the sense of time. Among which, program 105 includes call instruction which activates call sub-routine devices and initiate a sub-routine in the set of program 102. The set of call position 108 and the set of program 102 constituted the Client-Server structure and indicated that call sub-routine device is the core of Client-Server structure which supports single machine programs.
FIG. 1D is a method of describing call sub-routine device from the standpoint of information. It emphasized the connection structure of call parameter transfer—virtual bus. It has the same function as indicated in FIG. 1A. However, in multiple machine environment, there must be external connections which seems similar to the single machine representation method of FIG. 1D.
Call sub-routine device is a shared hardware structure and must be operated in time division. The operating process of call sub-routine device comprises three aspects:                call position—call parameter—sub-routine module        
Among which, call position initiates call sub-routine device. Call parameter is the object to be transferred. Sub-routine module is an operational structure. During entering, there is a position protection, and sub-routine module is incorporated with return instruction.
FIG. 1E is the usual technique of hardware interrupt. Interrupt signal 106 is connected to the interrupt pin of computer, CPU 107 so that computer CPU 107 can be turned to interrupt program.
As indicated in FIG. 1F, the effects on the program structure made by interrupt are the quit of original program 101, quit position protected and interrupt program 109 entered, interrupt program 109 quitted with interrupt recovery instruction, and recovered operation of original program 101. Obviously, interrupt structure is similar to call instruction in many aspects. Among which, interrupt vector is similar to call parameter, interrupt program is similar to sub-routine. The discrimination between interrupt and call lies on the fact that interrupt position is of no relation with interrupted program, whereas call position has an ordered relation with the contextual events of original program.
There are three elements in the process of executing interrupt structure:                Interrupt position—interrupt hardware structure externally initiated, to locate the interrupt location of program.        Interrupt vector—indicates the entry of interrupt program.        Entry of interrupt program—vector interrupted program, recovering original program by interrupt recover instruction.        
As for the computer hardware, the characteristics of interrupt is similar to that of call instruction and featured with the effects of embedded programs except that the front ends of processing are different. This fact denotes that the most hardware parts of call instruction device can be shared by both call instruction and interrupt. Whereas on the processing on program device before entering call sub-routine, the difference between them had been treated separately as the processing off known ordered events and external random events. Therefore, it is evident that call sub-routine device of single machine is shared by both ordered events and random events.
FIG. 2A is the schematic diagram of sequence net and encapsulation. The sequence net computer in previous invention is a kind of parallel program with distributed structure (China Patent Pending No. 00119472.9). As indicated in FIG. 2A, it is featured with distributed data token structure 204 and N+1 (in the figure N=3) program flows 210Ps, 211P1, 212P2, 213P3. Distributed data token 204 performs internally the consistency operation of data and token. Among which, each distributed data token 204 comprises a consistency token instruction 201, a source data token instruction 202, and multiple-targeted data token instruction 203. Program P1-P3 are composed with source data token instruction 202 and target data token 203. Consistency program Ps is composed by consistency token instruction 201. The read and write operation made to data token instruction by each program is constrained in local area.
Sequence net is performed by operations independently driven by N+1 programs. The principles of operations are as follows:
1. In case of specific instruction of write-data, program writes data into data token, and producing a source token. The program is going on. Therefore source data token of sequence net is generated.
2. In case of specific instruction of read-data, program reads data from local data token. Test to token with same address is performed by hardware. If valid, the program goes on. If invalid, the program is suspended until the appearance of valid data. Hence, target data token of the sequence net is generated.
3. In case of consistency instruction, data token consistency operation of the distributed data token is executed. Consistency operation is the transmission of data and token to destination. The consistency instruction tests the token value in consistency operation (in transmission). If the test is invalid, consistency instruction will be repeated automatically until the appearance of valid source (data) token. If the test is valid, the consistency instruction quits and the program is going on continuously. Therefore, the consistency token of sequence net is generated.
Sequence Net Encapsulation
By definition of sequence net, interconnection and synchronization of multiple programs can be done within the sequence net itself Therefore, if N+1 programs of sequence net went into operation, sequence net can perform the computation for sequence net itself and no help from outside was needed. Hence sequence net can be encapsulated in the form of N+1 program sections.
Interrupted Characteristics of Sequence Net
By the working principle of sequence net, sequence net is a parallel program. Suspension occurred in any branch will cause quit of sequence net. However, no fault will be occurred in sequence net. Once the program is recovered, the sequence net can be going on continuously. Therefore interrupt in any branch of sequence net can be allowed. When N+1 branches are interrupted simultaneously and a new sequence net is constituted by the N+1 interrupted programs, then it is obvious that a sequence net can be interrupted by another sequence net.
Hence, sequence net is featured with two important characteristics of operations:                Capable of being encapsulated: when N+1 sequence net branches are initiated, the sequence net can perform by itself the functions of parallel modules.        Capable of being interrupted: Interruption to any sequence net in operating condition by another sequence net is allowed. The correctness of sequence net operation is not affected by interrupt.        
It had been indicated in previous invention that in the past most operable parallel processing computers could actually support one parallel level sequence net. It is evident that parallel processing computers could not meet requirements of diversified application models, So its applications are seriously constrained. Sequence net of this invention has inaugurated the support to multiple sequence nets. The interconnection between multiple sequence nets is realized by the structure of call Sub SN.